1. Field of the Invention
The present invention relates to a semiconductor package including a plate-like mount, a semiconductor chip mounted on the plate-like mount, a plurality of leads electrically connected to the semiconductor chip, and an enveloper sealing and encapsulating the plate-like mount, semiconductor chip, and inner portions of the leads.
Also, the present invention relates to a production process for manufacturing such a semiconductor package.
2. Description of the Related Art
For example, as disclosed in Japanese Patent Publication No. 2714037 corresponding to Japanese Laid-Open Patent Publication (KOKAI) No. HEI-01-087535, a lead frame is used to manufacture an electronic package having a plurality of leads.
In particular, the lead frame includes an outer frame section, a plurality of islands or plate-like mounts, and a set of lead sections associated with each plate-like mount, and the plate-like mounts and lead sections are suitably supported by the outer frame section. A semiconductor chip is mounted on each plate-like mount, and is electrically connected to inner end portions of the lead sections in each set through the intermediary of bonding-wires.
Then, each plate-like mount, the semiconductor chip mounted thereon, and the inner end portions of the lead sections are sealed and encapsulated in a mold resin or enveloper, resulting in production of a plurality of electronic packages on the lead frame. Thereafter, the individual electric packages are cut and separated from the lead frame, using a punching machine.
In this type electronic package, especially a MOSFET package, there is a demand for miniaturization of the electronic package, whereas there is a demand for use of a large-sized semiconductor chip in the electronic package to thereby obtain a high power performance. To deal with these contradictory demands, it is proposed that the inner ends of the lead sections are directly and electrically connected to the semiconductor chip, as disclosed in Japanese Laid-Open Patent Publication (KOKAI) No. HEI-11-354702, and Japanese Patent Publication No. 3240292 corresponding to Japanese Laid-Open Patent Publication (KOKAI) No. 2000-114445.
Namely, it is possible to compactly arrange the lead sections with respect to the semiconductor chip mounted on the plate-like mount, due to the direct connection between the semiconductor chip and the inner ends of the lead sections. However, this arrangement of the lead sections fails to obtain a sufficiently high power performance in the electronic package, as discussed in detail hereinafter.
In short, conventionally, there are no proposals for successively dealing with the aforesaid contradictory demands.